Description: Verification Methodology Manual for SystemVerilog Please note: this item is printed on demand and will take extra time before it can be dispatched to you (up to 20 working days). Author(s): Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale Format: Paperback Publisher: Springer-Verlag New York Inc., United States Imprint: Springer-Verlag New York Inc. ISBN-13: 9781461498131, 978-1461498131 Synopsis Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.
Price: 78.34 GBP
Location: Aldershot
End Time: 2024-11-05T09:03:52.000Z
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Book Title: Verification Methodology Manual for SystemVerilog
Number of Pages: 503 Pages
Language: English
Publication Name: Verification Methodology Manual for Systemverilog
Publisher: Springer-Verlag New York Inc.
Publication Year: 2014
Subject: Engineering & Technology, Computer Science, Physics
Item Height: 235 mm
Item Weight: 795 g
Type: Textbook
Author: Andy Nightingale, Eduard Cerny, Janick Bergeron, Alan Hunter
Subject Area: Electrical Engineering
Item Width: 155 mm
Format: Paperback
