Description: SystemVerilog for Verification by Chris Spear, Greg Tumbush Estimated delivery 3-12 business days Format Paperback Condition Brand New Description Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. Publisher Description Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students understanding of the material. Other features of this revision include:New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulatorsSystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers. Author Biography Chris Spear has been working in the ASIC design and verification field for 30 years. He started his career with Digital Equipment Corporation (DEC) as a / CAD Engineer on DECsim, connecting the first Zycad box ever sold, and then a hardware Verification engineer for the VAX 8600, and a hardware behavioral simulation accelerator. He then moved on to Cadence where he was an Application Engineer for Verilog-XL, followed by a stint at Viewlogic. Chris is currently employed at Synopsys Inc. as a Verification Consultant, a title he created a dozen years ago. He has authored the first and second editions of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Chris earned a BSEE from Cornell University in 1981. In his spare time, Chris enjoys road biking in the mountains and traveling with his wife.Greg Tumbush has been designing and verifying ASICs and FPGAs for 13 years. After working as a researcher in the Air Force Research Labs (AFRL) he moved to beautiful Colorado to work with Astek Corp as a Lead ASIC Design Engineer. He then began a 6 year career with Starkey Labs, AMI Semiconductor, and ON Semiconductor where he was an early adopter of SystemC and SystemVerilog. In 2008, Greg left ON Semiconductor to form Tumbush Enterprises, LLC where he has been consulting clients in the areas of design, verification, and backend to ensure first pass success. He is also a part time Instructor at the University of Colorado, Colorado Springs where he teaches senior and graduate level digital design and verification courses. He has numerous publications which can be viewed at Greg earned a Ph.D. from the University of Cincinnati in 1998. Details ISBN 1489995005 ISBN-13 9781489995001 Title SystemVerilog for Verification Author Chris Spear, Greg Tumbush Format Paperback Year 2014 Pages 464 Edition 3rd Publisher Springer-Verlag New York Inc. GE_Item_ID:137612378; About Us Grand Eagle Retail is the ideal place for all your shopping needs! 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Price: 81.91 USD
Location: Fairfield, Ohio
End Time: 2024-11-21T03:35:50.000Z
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Restocking Fee: No
Return shipping will be paid by: Buyer
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ISBN-13: 9781489995001
Book Title: SystemVerilog for Verification
Number of Pages: Xliv, 464 Pages
Language: English
Publication Name: Systemverilog for Verification : a Guide to Learning the Testbench Language Features
Publisher: Springer
Subject: Hardware / General, Cad-Cam, Electronics / Circuits / Integrated, Electronics / Circuits / General, Programming / Object Oriented, Logic Design
Publication Year: 2014
Type: Textbook
Item Weight: 27.2 Oz
Author: Chris Spear, Greg Tumbush
Subject Area: Computers, Technology & Engineering
Item Length: 9.3 in
Item Width: 6.1 in
Format: Trade Paperback
